1. Field of the Invention
The present invention relates to an IC tester for testing a logical IC device having at least one memory built therein.
2. Description of the Related Art
Conventional logical IC's have a mainly logical circuits formed therein and there are also logical IC's each having a memory or memories built therein in addition to logical circuits. In these types of IC's, terminals leading to the memory can be all connected to external pins by switching the mode of operation from a logical circuit test mode to a memory test mode. Accordingly, the incorporated memory can be tested independently of the logical circuits by setting the memory test mode.
FIG. 1 (Prior Art) shows the construction of a conventional IC tester for testing IC's of this kind. The IC tester is provided with a logic test pattern generator 10 for generating logic test patterns for testing a logical circuit of an IC 36 under test and a memory test pattern generator 20 for generating memory test patterns for testing a memory. The IC tester is adapted to be switchable between the logical circuit test mode and the memory test mode so as to be able to test the logical circuit and the memory independently of each other.
The logic test pattern generator 10 comprises a logic test pattern memory 10A, a waveform control pattern memory 10B and a logical comparison control pattern memory 10C. The logic test pattern memory 10A has logic test pattern data stored therein for performing a logic test on the IC 36 under test and the pattern data is read out therefrom as logic test pattern data PLA of plural channels which are supplied through OR circuits 61 to a waveform formatter 31. Generally, the number of channels is set to be equal to the number of pins of an IC under test which is deemed to have the largest number of pins among IC's to be tested. The waveform control pattern memory 10B has waveform control pattern data for logic test stored therein and the logic test waveform control pattern data is read out therefrom as logic test waveform control pattern data PB of plural channels which are supplied to a waveform controller 32. The logical comparison control pattern memory 10C has logical comparison control pattern data for logic test stored therein and the logic test logical comparison control pattern data is read out therefrom as logic test logical comparison control pattern data PC of plural channels which are supplied to a logical comparison part 33.
The waveform formatter 31 generates a logical waveform for testing the logical circuit of an IC 36 under test, based on the logic test pattern data PLA read out of the logic test pattern memory 10A and provided via OR circuits 61 and a timing signal TS provided from a timing generator 40. The logical waveform is supplied as a logic test pattern signal to the IC 36 via a group of drivers 35. The waveform control pattern data PB read out of the waveform control pattern memory 10B is input into the waveform controller 32 to effect ON-OFF control of each driver of the driver group 35. That is, when a logic test pattern signal is applied to terminal pins of the IC under test 36, the corresponding drivers are controlled to turn the ON state (i.e. the activated state) and when a response signal is taken out of the IC 36, the driver is controlled to enter the OFF state (i.e. the state of a high output impedance).
The comparison control pattern data PC read out of the logical comparison control pattern memory 10C is input into the logical comparison part 33, wherein it is controlled on a bitwise basis (i.e. for each pin) whether or not to make a comparison between the logic of the response output signal from the IC under test 36, decided by a logic decision comparator group 37, and expected value pattern PD derived from the logic test pattern data PLA. Reference numeral 38 denotes a failure analysis memory for storing the results of logical comparison from the logical comparison part 33.
The timing generator 40 applies the timing signal TS to the waveform formatter 31, the waveform controller 32 and the logical comparison part 33 to time their operations. The timing generator 40 also applies an operating clock CK to a sequence controller 50. Based on the operating clock CK supplied from the timing generator 40, the sequence controller 50 generates a control signal such as a pattern address, which is applied to the test pattern memory 10A, the waveform control pattern memory 10B and the logical comparison control pattern memory 10C to control their readout sequences to read out therefrom the respective pieces of pattern data PLA, PB and PC.
Also in the case of testing a memory in the IC 36, the control signal such as a pattern address, provided from the sequence controller 50, is used to read out the waveform control pattern data PB and the comparison control pattern data PC from the logic test pattern generator 10 and, in this instance, the logic test pattern data PLA is not read out, but instead memory test pattern data PMA is read out of the memory test pattern generator 20 by the same control signal. The memory test pattern data PMA is composed of address pattern data which is applied to the address input pins of the IC under test 36, input data pattern data which is provided to the data input pins of the IC 36 and control pattern data which controls whether to effect a write or read in each test cycle. These pieces of data are respectively provided at predetermined ones of output terminals Q.sub.0 to Q.sub.i of the memory test pattern generator 20 irrespective of the pin array of the IC under test 36.
The memory test pattern data PMA is selected by a pattern selector 25, for each pin, in accordance with terminal select addresses set in a pattern select register 26 and is provided via the OR circuit 61 to the waveform formatter 31. The pattern selector 25 is made up of multiplexers MP.sub.1 to MP.sub.n provided corresponding to pins T.sub.1 to T.sub.n of the IC under test 36 and each having connected thereto all the output terminals Q.sub.0 to Q.sub.i of the memory test pattern generator 20. The pattern select register 26 is made up of terminal address registers R.sub.1 to R.sub.n connected to control terminals C of the multiplexers MP.sub.1 to MP.sub.n, respectively. Prior to the test of the IC 36 an address is set in each of the terminal address registers R.sub.1 to R.sub.n for specifying any one of the output terminals Q.sub.1 to Q.sub.i which is to be selected by each of the multiplexers MP.sub.1 to MP.sub.n in accordance with the pin array of the IC 36. Thus, selected pieces of the address pattern data and the input data pattern data are provided to the address and input pins of the IC under test 36 according to the setting of the pattern select register 26. The sequence controller 50 provides to an inhibit terminal INH of the pattern selector 25 a control signal GS which represents whether the test currently under way is a logic test or memory test. When the control signal GS is, for example, a "1" representing a logic test, the pattern selector 25 inhibits all of its outputs, preventing erroneous outputting of signals from the memory test pattern generator 20.
Conventionally, during the memory test, the memory test pattern data PMA selected by the pattern selector 25 for each pin is provided to the waveform formatter 31, and at the same time, the waveform control pattern data PB and the comparison control pattern data PC are provided to the waveform controller 32 and the logical comparison part 33 from the logic test pattern generator 10, effecting waveform control and control of the logical comparison. The waveform control and the logical comparison must be conducted for each pin, and consequently, when the positions of pins for testing a memory differ with the types of IC's to be tested, it is necessary that programs for generating the waveform control pattern data PB and the comparison control pattern data PC be prepared for each type.
In practice, some memory built-in type logic IC devices have such arrangements of terminals as shown in FIGS. 2, through 4. In the IC 36 depicted in FIG. 2 there are arranged memory test address input pins 361 on a side A containing a first pin T.sub.1, memory test data output pins 362 on a side B, and memory test data input pins 363 and a read/write control signal input pin 364 on a side D containing a last pin T.sub.n. These pins 361 through 364 are connected to a memory 36M incorporated in the IC 36. The other remaining pins are those for a logic circuit 36L shown as an area except the memory 36M in the IC 36.
The IC depicted in FIG. 3 has memory test data I/O pins 365 arranged on the side A containing the first pin T.sub.1, the read/write control signal input pin 364 on the side B and the memory test address input pins 361 on the side D.
The IC 36 shown in FIG. 4 has built therein two memories 36M1 and 36M2. In this instance, there are arranged the address input pins 361 of the memory 36M1 and the data I/O pins 365 of the memory 36M2 on the side A, the data output pins 362 of the memory 36M1 and the read/write control signal input pin 364 of the memory 36M2 on the side B and the data input pins 363 and the read/write control signal input pin 364 of the memory 36M1 and the address input pins 361 of the memory 36M2 on the side D.
In the case where the arrangement of pins differs with the types of IC's as mentioned above, it is necessary in the prior art to change the setting of the pattern select register 26 for each type and to prepare pattern generation programs of the waveform control pattern memory 10B and the logical comparison control pattern memory 10C for each type. This inevitably calls for increased storage capacities of the test pattern memory 10B and the logical comparison control pattern memory 10C. Besides, it is troublesome to manage the pattern generation programs prepared for each type of the IC to be tested.